1. Field of the Invention
The present invention relates to integrated circuit chip-testing procedures, and particularly to a circuit and method for increasing scan cell observability of response compactors.
2. Description of the Related Art
While scan-based testing is widely adopted, a large number of scan cells coupled with a large set of scan patterns reflect into an inflated test data volume and prolonged test application time. To alleviate the associated test costs, test data compression solutions are employed.
In such a scheme, a few number of scan-in channels drive a larger number of internal scan chains through a decompression block, while the responses collected from the internal scan chains are taken through a compactor block that drives a fewer number of scan-out channels. Due to on-chip stimulus expansion on the input side and to on-chip response compaction on the output side, test data volume is reduced. Furthermore, driving a larger number of internal scan chains from a fewer number of scan channels reduces the depth of the scan chains, decreasing the number of shift (scan) operations per scan pattern, and hence shortening the test application time.
While response compaction reduces the size of expected vectors that need to be stored on tester memory, the consequent information loss inevitably reflects into loss in test quality. Certain errors that are observable in original scan responses may become unobserved in the compacted responses. Observability loss may be a consequence of multiple errors masking out the effect of each other, producing the expected values, or of the ambiguity induced by unknown response bits (x's) that may take on either binary value upon arbitrary initialization.
Uninitialized memory elements such as RAMs, multi-cycle paths or bus contentions in a design constitute potential sources for unknown values, which may propagate into a scan cell upon the application of a test pattern. These unknown response bits create a multiplicity of expected vectors, preventing an error from manifesting at the compactor outputs. A scan slice consists of one scan cell from each scan chain such that the distance of these scan cells to the scan-out pin of the associated chain are identical. Thus, the scan cells that are in the same scan slice with another scan cell that has captured an unknown bit may become unobservable when a response compactor is utilized.
Sequential circuitries, such as MISRs, can be utilized for compressing scan responses into a signature to be observed at the end of the test application process. Unknown response bits corrupt the MISR content, however, if they propagate into the MISR. The fact that a single x corrupts the MISR signature stems from the sequential nature of a MISR in accumulating its signature. An x-masking circuitry, capable of delivering per-scan or per-pattern replacement of response x's with known constant values based on control bits delivered from the ATE, can be utilized along with a MISR. In the presence of many unknown bits, however, their must-be-perfect masking may disable the observation of most of the scan cells, which is also referred to as over-masking, reducing the effectiveness of test patterns. Therefore, these selective masking approaches also incur area and test data volume overhead, wherein the magnitude of this overhead depends on the extent of the desired flexibility in masking scan chains and/or cycles.
Combinational, mostly XOR-based, solutions are therefore widely used for response compaction. Some of these techniques build the response compactor based on fault sensitization information under a particular fault model assumption while response unknown bit and unmodeled defect coverage issues are overlooked. Test set and fault model independent techniques have also been proposed. However, each one of these techniques bears a particular unknown bit resistance characteristic. The density and the distribution of unknown response bits determine the test quality delivered by these schemes.
The synthesis of the response compactor based on a given set of test patterns and, thus, the knowledge regarding the position of the unknown bits helps maximize scan cell observability. Design changes in the form of ECOs (Engineering Change Orders) late in the design cycle, however, doom this type of technique, as the design change necessitates regeneration of test patterns, and hence the re-synthesis of the compactor, which may not be afforded towards the end of a tape-out process.
A previously proposed technique, referred to as response shaper, is capable of delaying only a single selected scan chain by only one cycle, constituting a special case of the proposed x-align block. It has been shown that utilization of even a simple single-output XOR tree along with a response shaper outperforms other more complex response compactors, such as convolutional compactors.
With the recent trend of testing designs faster than at-speed, wherein small delay defects are targeted even on shorter paths, the test is applied at a frequency that exceeds the functional speed. A resulting problem is that timing exceptions are raised on the longer paths that cannot meet the set-up constraints, resulting in x-heavy test responses.
In fact, for an unknown-heavy design with a large number of scan chains, and/or with deep scan chains, the single-cycle-delay in a single-scan-chain capability falls short in delivering reasonable scan cell observability enhancements. While the selection of the only chain to be delayed constitutes a less challenging problem for which all possible solutions can be simply enumerated, further significant test quality enhancements can be reaped through the generalization of the challenging x-alignment problem.
Accordingly, a generic-hardware solution that is nevertheless capable of adapting to the distribution of unknown bits for any given set of scan patterns is the key to attaining heightened levels of test quality while delivering practicality. This adaptiveness can be achieved by exploiting the built-in reconfigurability of the generic hardware through the insertion of proper control bits. Manipulation of x distribution through such a reconfigurability alleviates the masking effect of x's. Thus, a circuit and method for increasing scan cell observability of response compactors solving the aforementioned problems is desired.